The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The present disclosure relates generally to data decoding, and more particularly to decoders for data encoded with a low density parity check (LDPC) encoder.
LDPC codes and decoders that are used to decode LDPC codes may be used in numerous applications and devices. For example, data storage, satellite communications, wireless communications, wire-line communications, and power-line communications are applications that may each use LDPC codes and LDPC decoders. Devices such as digital camera flash memory storage, satellites, mobile phones, and other mobile devices may also each use LDPC codes and LDPC decoders.
LDPC codes may be used for correcting errors in information transmitted in a noisy communications or data storage channel. The information may be encoded (by a LDPC encoder) prior to transmission and then subsequently decoded (by a LDPC decoder) when received. Conventional hard decoding LDPC techniques are typically two-state systems, in which bits in an incoming code are assigned to one of two binary states. Improved decoding results can be achieved using soft information, such as probability distributions. However, storing and processing soft information can be very demanding on processor and memory resources.
Previous LDPC techniques typically determine whether to flip a bit based on whether a given number of checks are unsatisfied. For example, values of one or more bits may be selected to be flipped based on which combination of bits is most likely to reduce the number of unsatisfied check nodes.